1. Field of the Invention
The invention relates to an error correction method and a memory device thereof, and more particularly, to a method that uses two-plane structure of the memory device for mixing the encoding/decoding to enhance the correcting ability and reliability and the memory device using such method.
2. Description of the Prior Art
Flash memories nowadays commonly use two-plane read/write technology to concurrently access different blocks so as to enhance the read/write efficiency. Due to the physical limitation of the times of read/write of a flash memory, each block therefore has different worn-out rate, adding the fact that the floating gates, which are mainly used as recording unit for NAND type flash memory, may go through program disturb when writing data, read disturb caused by too many access times, and influences by the defects, environment, and temperature, quite a few generic floating gate faults exist in every flash memory. In a common situation, a single level cell (SLC) memory has generic fault rate falling within 10−9˜10−11 and a multi level cell (MLC) memory has generic fault rate falling within 10−5˜10−7.
To deal with the data error caused by the floating gate fault, error correction code (ECC) is extensively used to lower the fault rate. For example, the ECC having 7 bits correctability may substantially improve the fault rate of a MLC flash memory to within 10−20˜10−35.
Please refer to FIG. 1 and FIG. 2. FIG. 1 is a schematic diagram of the recording format of a page 1 of a NAND flash memory and FIG. 2 is a schematic diagram of a flow chart illustrating the encoding and decoding procedures of ECC. A NAND flash memory is regulated to have minimum writing unit as a page when programming, where the page 1 includes d bytes user data 11, n bytes ECC 12, and an information area 13. The information area 13 is used to store the logical block address (LBA) of the memory, the erase times, and some firmware information. The ECC 12 is generated according to the user data 11 and the Bose-Chaudhuri-Hocquenghem (BCH) algorithm is the most common ECC encoding/decoding algorithm applied to NAND flash memory. Once the ECC 12 is generated, it can be used to correct up to T error bits for the user data 11 and the ECC 12 itself in page 1 (totally d+n bytes), where T is relevant to the length n of the ECC 12.
Please refer to FIG. 2. As previously mentioned, during the encoding process 100, the n bytes ECC 12 is first generated according to the user data 11 in Step 102 and then in Step 104, the user data and the ECC 12 are written to the page 1 of the memory. To ensure the correctness of the data in page 1 before they can be outputted and used, the ECC 12 is used to detect and correct the user data 11 as shown in the decoding process 200. The user data 11 and the ECC 12 are read from the page 1 in Step 202 and then in Step 204, the ECC 12 is used for detecting if there is any error bit in the user data 11. If no error bit exists, the correct user data 11 is outputted to a processing unit in Step 206. If there are error bits detected in Step 204, it should further be checked if the number of the error bits is fewer than the error correctability (T bits) of the ECC 12. If the number of the detected error bits is fewer than T bits, Step 208 is then performed as the ECC 12 is used to correct all the error bits of the user data 11. If the number of the detected error bits is more than T bits, then the ECC algorithm fails and fault occurs in the page 1 (Step 210).
Although the ECC is commonly used to deal with the error bits of the page 1, the error correctability of the ECC may no longer effective when the number of error bits of the page 1 will be easily exceeding T bits as the memory keeps being read/written, accompanying any aforementioned situations. The fault rate of the memory is inevitably increasing to harm its credibility. On the other hand, although the error correctability (T bits) may be enhanced by increasing the length of the ECC 12, it means more space should be used for the ECC 12, which decreases overall memory capacity.